# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |

  define void @fadd_v4f32(<4 x float>* %a, <4 x float>* %b, <4 x float>* %c) { entry: ret void }
  define void @fadd_v2f64(<2 x double>* %a, <2 x double>* %b, <2 x double>* %c) { entry: ret void }

  define void @fsub_v4f32(<4 x float>* %a, <4 x float>* %b, <4 x float>* %c) { entry: ret void }
  define void @fsub_v2f64(<2 x double>* %a, <2 x double>* %b, <2 x double>* %c) { entry: ret void }

  define void @fmul_v4f32(<4 x float>* %a, <4 x float>* %b, <4 x float>* %c) { entry: ret void }
  define void @fmul_v2f64(<2 x double>* %a, <2 x double>* %b, <2 x double>* %c) { entry: ret void }

  define void @fdiv_v4f32(<4 x float>* %a, <4 x float>* %b, <4 x float>* %c) { entry: ret void }
  define void @fdiv_v2f64(<2 x double>* %a, <2 x double>* %b, <2 x double>* %c) { entry: ret void }

...
---
name:            fadd_v4f32
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1, $a2

    ; P5600-LABEL: name: fadd_v4f32
    ; P5600: liveins: $a0, $a1, $a2
    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)
    ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)
    ; P5600: [[FADD_W:%[0-9]+]]:msa128w = FADD_W [[LD_W]], [[LD_W1]]
    ; P5600: ST_W [[FADD_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)
    ; P5600: RetRA
    %0:gprb(p0) = COPY $a0
    %1:gprb(p0) = COPY $a1
    %2:gprb(p0) = COPY $a2
    %3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
    %4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
    %5:fprb(<4 x s32>) = G_FADD %3, %4
    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
    RetRA

...
---
name:            fadd_v2f64
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1, $a2

    ; P5600-LABEL: name: fadd_v2f64
    ; P5600: liveins: $a0, $a1, $a2
    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
    ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)
    ; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)
    ; P5600: [[FADD_D:%[0-9]+]]:msa128d = FADD_D [[LD_D]], [[LD_D1]]
    ; P5600: ST_D [[FADD_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)
    ; P5600: RetRA
    %0:gprb(p0) = COPY $a0
    %1:gprb(p0) = COPY $a1
    %2:gprb(p0) = COPY $a2
    %3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
    %4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
    %5:fprb(<2 x s64>) = G_FADD %3, %4
    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
    RetRA

...
---
name:            fsub_v4f32
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1, $a2

    ; P5600-LABEL: name: fsub_v4f32
    ; P5600: liveins: $a0, $a1, $a2
    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)
    ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)
    ; P5600: [[FSUB_W:%[0-9]+]]:msa128w = FSUB_W [[LD_W]], [[LD_W1]]
    ; P5600: ST_W [[FSUB_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)
    ; P5600: RetRA
    %0:gprb(p0) = COPY $a0
    %1:gprb(p0) = COPY $a1
    %2:gprb(p0) = COPY $a2
    %3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
    %4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
    %5:fprb(<4 x s32>) = G_FSUB %3, %4
    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
    RetRA

...
---
name:            fsub_v2f64
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1, $a2

    ; P5600-LABEL: name: fsub_v2f64
    ; P5600: liveins: $a0, $a1, $a2
    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
    ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)
    ; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)
    ; P5600: [[FSUB_D:%[0-9]+]]:msa128d = FSUB_D [[LD_D]], [[LD_D1]]
    ; P5600: ST_D [[FSUB_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)
    ; P5600: RetRA
    %0:gprb(p0) = COPY $a0
    %1:gprb(p0) = COPY $a1
    %2:gprb(p0) = COPY $a2
    %3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
    %4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
    %5:fprb(<2 x s64>) = G_FSUB %3, %4
    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
    RetRA

...
---
name:            fmul_v4f32
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1, $a2

    ; P5600-LABEL: name: fmul_v4f32
    ; P5600: liveins: $a0, $a1, $a2
    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)
    ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)
    ; P5600: [[FMUL_W:%[0-9]+]]:msa128w = FMUL_W [[LD_W]], [[LD_W1]]
    ; P5600: ST_W [[FMUL_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)
    ; P5600: RetRA
    %0:gprb(p0) = COPY $a0
    %1:gprb(p0) = COPY $a1
    %2:gprb(p0) = COPY $a2
    %3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
    %4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
    %5:fprb(<4 x s32>) = G_FMUL %3, %4
    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
    RetRA

...
---
name:            fmul_v2f64
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1, $a2

    ; P5600-LABEL: name: fmul_v2f64
    ; P5600: liveins: $a0, $a1, $a2
    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
    ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)
    ; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)
    ; P5600: [[FMUL_D:%[0-9]+]]:msa128d = FMUL_D [[LD_D]], [[LD_D1]]
    ; P5600: ST_D [[FMUL_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)
    ; P5600: RetRA
    %0:gprb(p0) = COPY $a0
    %1:gprb(p0) = COPY $a1
    %2:gprb(p0) = COPY $a2
    %3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
    %4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
    %5:fprb(<2 x s64>) = G_FMUL %3, %4
    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
    RetRA

...
---
name:            fdiv_v4f32
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1, $a2

    ; P5600-LABEL: name: fdiv_v4f32
    ; P5600: liveins: $a0, $a1, $a2
    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load (<4 x s32>) from %ir.a)
    ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load (<4 x s32>) from %ir.b)
    ; P5600: [[FDIV_W:%[0-9]+]]:msa128w = FDIV_W [[LD_W]], [[LD_W1]]
    ; P5600: ST_W [[FDIV_W]], [[COPY2]], 0 :: (store (<4 x s32>) into %ir.c)
    ; P5600: RetRA
    %0:gprb(p0) = COPY $a0
    %1:gprb(p0) = COPY $a1
    %2:gprb(p0) = COPY $a2
    %3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
    %4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
    %5:fprb(<4 x s32>) = G_FDIV %3, %4
    G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
    RetRA

...
---
name:            fdiv_v2f64
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1, $a2

    ; P5600-LABEL: name: fdiv_v2f64
    ; P5600: liveins: $a0, $a1, $a2
    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
    ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load (<2 x s64>) from %ir.a)
    ; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load (<2 x s64>) from %ir.b)
    ; P5600: [[FDIV_D:%[0-9]+]]:msa128d = FDIV_D [[LD_D]], [[LD_D1]]
    ; P5600: ST_D [[FDIV_D]], [[COPY2]], 0 :: (store (<2 x s64>) into %ir.c)
    ; P5600: RetRA
    %0:gprb(p0) = COPY $a0
    %1:gprb(p0) = COPY $a1
    %2:gprb(p0) = COPY $a2
    %3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
    %4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
    %5:fprb(<2 x s64>) = G_FDIV %3, %4
    G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
    RetRA

...
